1. Field of the Invention
The present invention relates to CMOS-type digital integrated circuits generally and more particularly to static random access memory cells.
2. Description of the Prior Art
Static random access memories (SRAMs) employ a number of cells, each for storing a single binary bit of information. Typical SRAM cell structures include what is commonly referred to as a four transistor, two-resistor (4T-2R) SRAM cell and what is commonly referred to as a six transistor (6T) SRAM cell. A (4T-2R) SRAM 100 cell is illustrated in (prior art) FIG. 1. SRAM cell 100 is shown to include four N-channel transistors 110, 112, 114, and 116, and two (load) resistors 120 and 122. The N-channel transistors and the load resistors may be constructed using single-crystal, poly-crystalline or amorphous semiconductor materials. Transistor 110 is configured as a transfer transistor with the source (or drain) (end of the channel) of the transistor connected to an (active-high) bit (input/output) line (BL), which is designated 130. The gate of transistor 110 is connected to an (active-high) word (control) line (WL) 132. The drain (or source) (end of the channel) of transistor 110 is coupled by resistor 120 to a power supply potential (Vcc) line 134.
Transistor 112 is configured as a pull-down transistor with the transistor source connected to circuit ground (Vss), with the transistor gate coupled by resistor 122 to power supply line 134, and with the transistor drain connected to the drain of transistor 110. Transistor 114 is also configured as a pull-down transistor with the transistor source connected to circuit ground, with the transistor gate connected to the drain of transistor 110, and with the transistor drain connected to the gate of transistor 112. Finally, transistor 116 is also configured as a transfer transistor with the transistor source connected to the gate of transistor 112, with the transistor gate connected to word line (WL) 132, and with the transistor drain connected to an (active-low) bit (input/output) line (/BL) 140. The lines 150 and 152 are connecting the cross-coupling gates and drains of the pull-down transistors.
A six transistor (6T) SRAM cell 200 is illustrated in (prior art) FIG. 2. SRAM cell 200 is shown to include four N-channel transistors designated 210, 212, 214, and 216, and two P-channel (load) transistors 220 and 222. The N-channel and P-channel transistors may be constructed using single-crystal, poly-crystalline or amorphous semiconductor materials. Transistor 210 is configured as a transfer transistor with the source (or drain) (end of the channel) of the transistor connected to an (active-high) bit (input/output) line (BL) 230. The gate of transistor 210 is connected to an (active-high) word (control) line (WL) 232. The drain (or source) (end of the channel) of transistor 210 is connected to a node which is connected to the source of transistor 220, to the drain of transistor 212, and to the gate of both transistors 214 and 222. Connected to another node is the gate of both transistors 220 and 212, the source of transistor 222, the drain of transistor 214, and the source of transistor 216. The drain of both transistors 220 and 222 are connected to a power supply potential (Vcc) line 234; the sources of both transistors 212 and 214 are connected to circuit ground (Vss). The gate of transistor 216 is connected to word line (WL) 232; the drain of the transistor is connected to an (active-low) bit (input/output) line (/BL) 240.
In the implementation of high density SRAMs, the cell size is one of the more critical parameters as it determines the total area of the memory array, and therefore the chip size. Heretofore for poly-silicon-resistor load (4T-2R) SRAM cells in the conventional planar layout, the size of the pull-down transistor 114 has accounted for a significant portion of the cell area. This is because heretofore the pull-down transistor 114 size had to be about three times that of the transfer transistor 116 to prevent the state of the cell from being upset when transfer transistor 116 is turned on when the state of the cell is being read.
The reader may find of interest U.S. Pat. Nos. 4,794,561 and 4,876,215 issued to Fu-Chieh Hsu, which disclose the static RAM cells of (prior art) FIGS. 1 and 2.
In laying out the memory cell with minimum area, one recent approach is to split the common word line (WL) (as in FIGS. 1 and 2) into two separate lines at both end of the memory cell to facilitate interconnecting the cross-coupled transistors within the memory cell (see, for
example, Itabashi et al., "A split wordline cell for 16 Mb SRAM using polysilicon sidewall contacts", pp.477-480, and Ohkubo et al., "16 Mb SRAM cell technologies for 2.0 V operation", pp.481-484, 1991 IEDM Technical Digest). Electrically, however, the two split word lines (WL) are connected together and are always driven simultaneously to conform to the circuit configuration of (prior art) FIGS. 1 and 2.
In another approach described in U.S. Pat. No. 5,047,979 issued to Wingyu Leung, a regenerative sense amplifier is used to minimize the SRAM cell area by allowing the use of much smaller pull-down transistors (See FIGS. 3 and 4 therein) without upsetting the state of the memory cell when it is being read.
The reduction in memory cell area in both the above approaches, however, is limited by the need to use two complementary (differential) bit lines (BL and /BL) in each memory cell.